ADISYN LTD — Investor Presentation 2024

Oct 23, 2024

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Transformational Semiconductor Solutions for Generative AI, Data Centres, Cybersecurity And Beyond

Presentation – October 2024

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Disclaimer

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This information contained in this presentation has been prepared by Adisyn Ltd (ACN 155 473 304) (ASX:AI1 or ‘the Company’) and makes statements about it as well as its subsidiaries, the presentation is for information purposes only. This presentation does not constitute financial product or investment advice or a recommendation to acquire AI1 shares and has been prepared without taking into account the objectives, financial situation or needs of individuals. This presentation does not purport to contain all of the information that a prospective investor may require to make an evaluation of the Company or its business activities. Before making an investment decision, prospective investors should consider the appropriateness of the information having regard to their own objectives, financial situation and needs and seek legal and taxation advice appropriate to their jurisdiction. AI1 is not licensed to provide financial product advice in respect of AI1 shares. Certain information in this presentation has been derived from third parties and though AI1 has no reason to believe that it is not accurate, reliable or complete it has not been independently audited or verified by AI1.

This information in this presentation should be read in conjunction with the Indicative Terms in the Appendix and the Company’s announcement dated 23 October 2024 (Announcement). The Company is optimistic about concluding the binding share purchase and for the Company proposed acquisition of 2D Generation. However, the Indicative Terms remain subject to negotiation by the parties and the execution of the binding share purchase agreement. Completion under the share purchase agreement will be subject to a number of conditions, including due diligence, as set out in Appendix. No binding agreement has been reached at this time and there is no certainty that the proposed acquisition will eventuate. The Indicative Terms in the appendix (and the Announcement) are preliminary, incomplete and non-binding and does not constitute a commitment to proceed with the proposed acquisition.

AI1, its subsidiaries and their respective logos, are trademarks or registered trademarks of AI1, or its subsidiaries. All other registered or unregistered trademarks mentioned in this presentation are the property of their respective owners, and no trademark rights to the same are claimed.

Financial Data - All dollar values are in AUD dollars (AUD or $) and are unaudited (unless otherwise presented). This presentation has been authorised for release on the ASX by the Board of Directors of AI1.

Future performance any forward looking statements, opinions and estimates provided in this presentation are based on assumptions and contingencies which are subject to change without notice, as are statements about market and industry trends, which are based on interpretations of current market conditions at the date of this presentation. Forward looking statements including projections, guidance on future earnings and estimates are provided as a general guide only and should not be relied upon as an indication or guarantee of future performance. An investment in AI1 shares is subject to investment and other known and unknown risks, some of which are beyond the control of AI1.

No representation or warranty, express or implied, is made as to the fairness, accuracy, completeness or correctness of the information, opinions and conclusions contained in this presentation. To the maximum extent permitted by law, Adisyn Ltd and its officers, employees, related bodied corporate and disclaim all liability, including, without limitation, any liability arising out of fault or negligence, for any loss arising from the use of the information contained in this presentation. In particular, no representation or warranty, express or implied is given as to the accuracy, completeness or correctness, likelihood of achievement or reasonableness of any forecasts, prospects or returns contained in this Presentation nor is any obligation assumed to update such information. Such forecasts, prospects or returns are by their nature subject to significant uncertainties and contingencies.

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Transformational AI and
Semiconductor
Opportunities
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Surge in Defence and
Cyber Security Activities
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Reliance on Data
Centres to Enable High
Performance Computing
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Leveraging Demand
for Our Services
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Sustained Revenue
Growth
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Enabling the next generation of high-performance, energy-efficient solutions for AI and data centres.

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2D Generation is partner in the EU’s ConnectingChips consortium with research partners including NVIDIA, IMEC, Valeo, Applied Materials, NXP, and Unity

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Dedicated to taking advantage of the explosive growth of AI and semiconductors by applying AI1's

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The Biggest Age of Computing…..Comes at a Cost

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Why we need the next generation of semiconductor technology in three graphs

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This explosion of data and generative AI being applied to it means more efficient semiconductors are critical for industry growth.

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What is an ‘Interconnect’?
2D Generation’s innovative technology centres
around the aim of improving the performance and
capabilities of the interconnect.
• An interconnect in a semiconductor refers to the
conductive pathways that connect different components
or regions within an integrated circuit (IC).
•
These interconnects are crucial for the functionality of the
IC as they facilitate the flow of electrical signals between
transistors, capacitors, resistors, and other elements on
the chip.
•
Interconnects can be made of various materials, typically
metals like aluminium or copper, and they can be
implemented in different layers within the semiconductor
structure.
•
As ICs have become more complex, with smaller and more
densely packed features, the design and materials used
for interconnects have evolved to address issues such as
resistance, capacitance, and signal integrity but have
reached scalability limitations.
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Enablin ‘More Moore’ g

“With each new technology generation, routing congestion and a dramatic signal delay (resulting from an increased resistancecapacitance (RC) product) become more and more problematic…”*

• For advanced process nodes, the ‘Interconnect’ is a bottleneck:

• Limiting clock and data transfer rates… ‘FORCED SPEED LIMITATION’

• Consumes a lot of power… ’COMPETING FOR ELECTRICITY’

• Major source of heat generation… ‘ADVANCED PREFORMANCE CAN BE ACHIEVED. MANY MORE TRANSISTORS CAN BE ADDED’

• "To continue scaling beyond the 2nm node, major breakthroughs in interconnect and contact design, as well as process technologies, are necessary.” (Applied Materials website)

• Graphene based solutions for the ‘INTERCONNECT’ are well defined, BUT UNTIL NOW THERE IS NO VIABLE SOLUTION

• From IMEC’s paper on Graphene for interconnects in 2021:

“While this study focuses on graphene transfer, a more ‘elegant’ way of depositing graphene would be direct growth on the metal template of interest. Growing high-quality graphene requires however high growth temperatures (900-1000°C) and can as such not be applied on interconnect-type of metals.”

• • Moore's Law is the principle that the speed and capability of computers can be expected to double every two years, as a result of increases in the number of transistors a microchip can contain

• https://www.imec-int.com/en/articles/promise-hybrid-graphenemetal-structures-advanced-interconnects

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Despite efforts, significant breakthroughs in this domain are still elusive

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1000 degrees) – a giant leap forward.

✓ – no Can be applied using existing industrial processes and equipment retooling.

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Reduced Signal Delay (RC Delay)

Enhanced Thermal Management

Improved Signal Integrity

2DG’s patented solution addresses the significant challenges facing the industry

Lower Power Consumption

Higher Density of Components

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2D Generation’s IMEC Agreement

Imec founded in 1984 is one of the world’s leading R&D hubs for nano and digital technologies. Imec employs around 5,000 expert scientists from more than 95 countries, unique infrastructure that includes a 2.5billion-euro 300mm semiconductor pilot line. Among Imec’s business partners are most of the manufacturers, suppliers, and fabless companies in the semiconductors industry including:

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2D Generation has signed a strategic cooperation agreement with Imec to validate the company technology in two aspects:

1. Physical tests of the graphene coating of several materials (metals and non-metals) and several usages (surfaces, structured wafers, and diffusion barrier).

2. Simulation to explore the benefits of the technology in a relevant context for product applications.

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ConnectingChips Collaboration

2D Generation Key Objective’s

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Working with the Best

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• Key Objective – “The CONNECTINGCHIPS ambition is to establish the next generation of AI computing and autonomous vehicles infrastructure based on SiP development.”

• The high level objective of CONNECTINGCHIPS is the development of power efficient high performance electronic, photonic, power, and RF chips and System on Chips (SoC) and their integration into System in Package (SiP) modules.

Project Scope:

Total budget: 110M€

Total European grant: 32 M€ Additional grants from the country’s innovation authorities – The Israeli Innovation Authority doubles the European grant.

Partners: 65 top companies and institutions (10 countries) Start: Q1 2025

2D Generation requires a grant of 200K € from Horizon Europe Chips (IA) + grant of 200K € from the Israeli Innovation Authority (approved)

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3/27

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Today 12/24 6/25 9/25

9/26

3/26

Experiments on 2DG ALD tools Pilot line in industrial Fab Feasibility (Partial MVP) – Demo, integration Feasibility (Full MVP) – Graphene in-situ deposition and growth of 2D ALD in Pilot line (FAB) using Atomic Layer Deposition graphene layers for advanced onto Industrial solutions/applications coupons and Graphene in-situ deposition patterned wafers using FAB ALD- 1[ST] LOT DOE using low temp conditions, up to 300°C Capping layer on Cu or Ru PROCESS TRANSFER- Coupons 1cm1 cm Wafer size Order new ALD tool New ALD tool ALD run installation and Commercial implementation development agreement with global semiconductor company with the aim of securing license fees going forward*

Experiments on 2DG ALD tools

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Four Patent Families:

Each patent application is directed to four aspects of the invention:

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ARYE KOHAVI
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MIRI KISH DAGAN PAUL RICH
VP R&D TECHNOLOGY LEADER
Paul Rich has more than 35 years of experience in the
semiconductor industry.
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EPHIE KOLTIN

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KEVIN CROFTON

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Thank you

Contact Details

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Blake Burton – Managing Director, AI1 investors@adisyn.com.au

Arye Kohavi – CEO, 2D Generation 2DGeneration.com

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David Tasker – IR / PR

dtasker@chapteroneadvisors.com.au

Michael Shaw-Taylor – Corporate Advisor mst@sandtoncapital.com.au

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