Skip to main content

AI assistant

Sign in to chat with this filing

The assistant answers questions, extracts KPIs, and summarises risk factors directly from the filing text.

Tower Semiconductor Ltd. Regulatory Filings 2009

Sep 25, 2009

7095_ffr_2009-09-25_db6fc971-8724-405f-83fe-ca1d07da9caf.zip

Regulatory Filings

Open in viewer

Opens in your device viewer

6-K 1 zk97292.htm Created by EDGAR Ease Plus (EDGAR Ease+) Project: \Backup\EDGAR Filing\Tower Semiconductor Ltd\97292\a97292.eep Control Number: 97292 Rev Number: 1 Client Name: Tower Semiconductor Ltd Project Name: 6-K Firm Name: Zadok-Keinan Ltd 6-K MARKER FORMAT-SHEET="Scotch Rule Top-TNR" FSL="Workstation" MARKER FORMAT-SHEET="Head Major Center Bold-TNR" FSL="Workstation"

FORM 6-K

MARKER FORMAT-SHEET="Head Minor Center-TNR" FSL="Workstation"

SECURITIES AND EXCHANGE COMMISSION

MARKER FORMAT-SHEET="Head Minor Center-TNR" FSL="Workstation"

Washington, D.C. 20549

MARKER FORMAT-SHEET="Head Sub 3 Left-TNR" FSL="Workstation"

For the month of September 2009 No. 5

MARKER FORMAT-SHEET="Head Major Center Bold-TNR" FSL="Workstation"

TOWER SEMICONDUCTOR LTD. (Translation of registrant’s name into English)

MARKER FORMAT-SHEET="Head Major Center Bold 1-TNR" FSL="Workstation"

Ramat Gavriel Industrial Park P.O. Box 619, Migdal Haemek, Israel 23105 (Address of principal executive offices)

MARKER FORMAT-SHEET="Para Large Indent Lv 0-TNR" FSL="Default"

Indicate by check mark whether the registrant files or will file annual reports under cover Form 20-F or Form 40-F.

Form 20-F x Form 40-F o

MARKER FORMAT-SHEET="Para Large Indent Lv 0-TNR" FSL="Default"

Indicate by check mark whether the registrant by furnishing the information contained in this Form is also thereby furnishing the information to the Commission pursuant to Rule 12g3-2(b) under the Securities Exchange Act of 1934.

Yes o No x

MARKER FORMAT-SHEET="Para Large Indent Lv 0-TNR" FSL="Workstation"

On September 25, 2009, the registrant announces Jazz Semiconductor Offers Industry’s First Reliability Modeling Tool to Optimize Device Performance-Lifetime Tradeoff.

MARKER FORMAT-SHEET="Para Large Indent Lv 0-TNR" FSL="Workstation"

This Form 6-K is being incorporated by reference into all effective registration statements filed by us under the Securities Act of 1933.

MARKER FORMAT-SHEET="Head Major Center Bold-TNR" FSL="Workstation"

SIGNATURES

MARKER FORMAT-SHEET="Para Large Indent Lv 0-TNR" FSL="Default"

Pursuant to the requirements of the Securities Exchange Act of 1934, the registrant has duly caused this report to be signed on its behalf by the undersigned, thereunto duly authorized.

MARKER FORMAT-SHEET="Signature (Single)" FSL="Workstation"

Date: September 25, 2009 TOWER SEMICONDUCTOR LTD. By: /s/ Nati Somekh Gilboa —————————————— Nati Somekh Gilboa Corporate Secretary

Jazz Semiconductor Offers Industry's First Reliability Modeling Tool to Optimize Device Performance-Lifetime Tradeoff

Extends design enablement offerings to customers for high reliability applications in Aerospace, Defense, Automotive and Medical markets

MARKER FORMAT-SHEET="Para Flush Lv 0-TNR" FSL="Workstation"

NEWPORT BEACH, Calif., September 25, 2009 – Jazz Semiconductor, Inc., a Tower Group Company (NASDAQ: TSEM, TASE: TSEM), today announced its pioneering Reliability Modeling Tool (RMT), offered free to its customers through its eBizz Web portal. The tool is critical for high reliability applications in aerospace, defense, automotive and medical markets. It allows designers to predict device degradation over the lifetime of the product, identify the vulnerable sub-systems related to device “aging,” and make design tradeoffs between operating lifetime and performance. In effect, the RMT reduces design spins or the product development time required for higher reliability systems. The RMT integrates into the existing Jazz design flow without the need to purchase any additional simulation tools, and is currently supported in Jazz’s 0.18-micron SiGe BiCMOS platform.

MARKER FORMAT-SHEET="Para Flush Lv 0-TNR" FSL="Workstation"

The RMT supplements an extensive design enablement infrastructure already in place at Jazz and underscores the company’s continued efforts to provide its customers with an analog and RF design environment that improves design optimization and reduces time-to-market. Jazz currently offers Monte Carlo statistical and PCM based models for its processes as well as fully scalable models and robust physical design tools for up front design optimization. This infrastructure used during the design phase, coupled with the RMT, allows circuit designers to truly design high-yielding and high-performance circuits capable of operating reliably for extended operating lifetimes.

MARKER FORMAT-SHEET="Para Flush Lv 0-TNR" FSL="Workstation"

“We differentiate ourselves with our advanced and proven design enablement solutions and are investing in expanding these offerings to our customer base for high reliability markets such as aerospace and defense as well as automotive and medical for a real time-to-market advantage,” said Dr. Samir Chaudhry, Director, Design Enablement at Jazz Semiconductor. “With the Reliability Modeling Tool, we have augmented our design for manufacturing platform with a tool that seamlessly integrates into existing design environments and enables accurate simulation of key degradation mechanisms so customers can design reliability into their products up front.”

MARKER FORMAT-SHEET="Para Flush Lv 0-TNR" FSL="Workstation"

Designing high performance RF and analog circuits often necessitates operating devices at the extreme edge of the allowable bias regime where a quantitative understanding of the impact on circuit performance is largely unknown. The RMT addresses this deficiency by enabling simulation of circuits with a user-specified “age” parameter. An optional second variable in the tool allows for the customization of the stress that the device is subjected to, enabling optimization of the performance-age tradeoff. The tool includes modeling of key degradation mechanisms, such as Hot Carrier Injection (HCI) for MOSFETs and reverse-beta degradation for SiGe NPN transistors. This was accomplished by fully characterizing the devices at varying degrees of accelerated stress conditions, and using physical extrapolation methods to map this stress to real-time “age” at operating voltages.

MARKER FORMAT-SHEET="Para Flush Lv 0-TNR" FSL="Workstation"

Availability The RMT is currently available to Jazz customers through eBizz on the company’s website for its 0.18um SiGe BiCMOS process (SBC18). The RMT will be available for other RF processes in the future.

MARKER FORMAT-SHEET="Para Flush Lv 0-TNR" FSL="Workstation"

About Tower Semiconductor, Ltd. and Jazz Semiconductor, Inc. Tower Semiconductor Ltd. (NASDAQ: TSEM, TASE: TSEM) is a global specialty foundry leader and its fully owned subsidiary Jazz Semiconductor, a Tower Group Company is a leader in Analog-Intensive Mixed-Signal (AIMS) foundry solutions. Tower and Jazz manufacture integrated circuits with geometries ranging from 1.0 to 0.13-micron and provide industry leading design enablement tools to allow complex designs to be achieved quickly and more accurately. Tower and Jazz offer a broad range of process technologies including Digital, Mixed-Signal and RFCMOS, HV CMOS, BCD, Non-Volatile Memory (NVM), Embedded NVM, MEMS, and CMOS Image Sensors. To provide world-class customer service, Tower and Jazz maintain two fabrication facilities in Israel and one in the U.S. with additional capacity available through manufacturing partnerships in China. For more information, please visit www.towersemi.com and www.jazzsemi.com.

MARKER FORMAT-SHEET="Para Flush Lv 0-TNR" FSL="Default"

Safe Harbor Regarding Forward-Looking Statements This press release includes forward-looking statements, which are subject to risks and uncertainties. Actual results may vary from those projected or implied by such forward-looking statements. A complete discussion of risks and uncertainties that may affect the accuracy of forward-looking statements included in this press release or which may otherwise affect Tower’s and Jazz’s business is included under the heading “Risk Factors” in Tower’s most recent filings on Forms 20-F, F-3, F-4 and 6-K, as were filed with the Securities and Exchange Commission (the “SEC”) and the Israel Securities Authority and Jazz’s most recent filings on Forms 10-K and 10-Q, as were filed with the SEC. Tower and Jazz do not intend to update, and expressly disclaim any obligation to update, the information contained in this release.

Company Contact: Media Contact:
Melinda Jarrell Lauri Julian
949/435-8181 949/715-3049
[email protected] [email protected]